1. Field of the Invention
The present invention relates to a semiconductor apparatus and, particularly, to a semiconductor apparatus in which a signal having an amplitude equal to or larger than a breakdown voltage of a transistor is input to the gate of the transistor.
2. Description of Related Art
Semiconductor micro-fabrication technology has been developed recently in order to reduce the chip size of a semiconductor apparatus. However, a transistor which is manufactured in a micro-fabrication process has a low breakdown voltage, and when a signal having the same voltage amplitude as it used to be is treated in a semiconductor apparatus which is fabricated in a micro-fabrication process, the amplitude of the signal exceeds the breakdown voltage of the transistor, which results in the breakdown of the semiconductor apparatus. Therefore, even if a device is micro-fabricated by a manufacturing process of the semiconductor apparatus, a micro-fabrication process cannot be used for a circuit that treats a signal with a large amplitude, which raises an issue that the chip size of the semiconductor apparatus cannot be sufficiently reduced.
To address such an issue, International Patent Publication No. WO97/08833 and Japanese Unexamined Patent Application Publication No. H11-176950 discloses one example of a technique for treating a signal having an amplitude equal to or larger than a breakdown voltage of a transistor. According to the technique disclosed therein, transistors are connected in multiple stages between a power supply terminal and a ground terminal, and a voltage applied to each transistor is suppressed to a breakdown voltage or lower. International Patent Publication No. WO97/08833 and Japanese Unexamined Patent Application Publication No. H11-176950 thereby form a circuit that treats a signal having an amplitude of equal to or larger than a breakdown voltage of a transistor
Further, Japanese Unexamined Patent Application Publication No. H07-78885 discloses a technique related to a level shifter that converts an input signal with a small amplitude into an output signal with a large amplitude. According to the technique disclosed therein, an inverter is made up of an NMOS transistor and a PMOS transistor that are connected in series between a power supply terminal and a ground terminal. Then, back-gate voltages of the NMOS transistor and the PMOS transistor are adjusted so as to invert the logic level of an output signal for an input signal having a smaller amplitude than a threshold voltage of the inverter, thereby controlling the threshold voltages of the NMOS transistor and the PMOS transistor of the inverter. Japanese Unexamined Patent Application Publication No. H07-78885 thereby allows the threshold voltage of the inverter to correspond to the amplitude of the input signal and inverts the logic level of the output signal having a larger amplitude than the input signal.